0.18 micron-英国威廉希尔公司

0.18 micron libraries

we have helped to revolutionize the foundry industry by offering comprehensive free-of-charge libraries from multiple vendors. in addition, hjtc also offers other libraries available on a fee basis.

artisan 0.18um library
standard cell

• 478 high-density standard cells
• 9-track cell architecture
• average cell density of 111k gates/sq.mm
• multiple drive strengths
• routable in 3, 4, 5 or more metal layers
• comprehensive design tool support
• process specific electrical and physical tuning

single-port synchronous sram generators

• optimized for high density and high speed
• flex-repair™ redundancy implementation option
  - includes separate fuse-box generator
  - supports flexible bist implementation
• broadly configurable to up to 512k bits:
  - 256 to 16k words deep (word increment = 2 x column mux)
  - 2 to 128 bits wide (bit increment = 1)
• user-configurable mask write option (1 to 36 bit segments)
• aspect ratio control for efficient floor planning (column mux options: 4, 8, 16)
• memory operation and data retention at low voltage and down to 0 mhz
• low active power and leakage-only standby current
• accurate timing and power models
• complete set of models supporting industry-leading design tools
• robust design practices and validation procedures ensure successful designs
• extensive silicon validation

dual-port synchronous sram generator

• optimized for high density and high speed
• two fully-independent read/write ports
• broadly configurable to up to 256k bits:
  - 128 to 8k words deep (word increment = 2 x column mux)
  - 2 to 128 bits wide (bit increment = 1)
• user-configurable mask write option (1 to 36 bit segments)
• aspect ratio control for efficient floor planning (column mux options: 4, 8, 16)
• memory operation and data retention at low voltage and down to 0 mhz
• low active power and leakage-only standby current
• accurate timing and power models
• complete set of models supporting industry-leading design tools
• robust design practices and validation procedures ensure successful designs
• extensive silicon validation

inline i/o

• 600 3.3v/5vt
• pad pitch: 60 um
• input: pull-up/pull-down,schmitt trigger,lvttl,cmos
• output: multiple current up tp 24ma with 3 slew rate options
• aspecial pads: clock, crystal oscillator, corner, power and ground

virtual silicon 0.18um library
standard cell

• 500 high performance standard cells
• 11-track cell architecture, performance optimized for 200~700 mhz
• average cell density of 90k gates/sq.mm
• multiple drive strengths
• layout using metal 1 only
• scan version of every flip-flop available
• fully contacted well ties
• accurate modeling and characterization for timing and power
• open architecture developers kit available

inline and staggered i/o

• 375 3.3v & 3.3v/5vt i/o pads
• pad pitch: 60um (in-line), 40um (staggered)
• multiple current drives up to 24ma
• input: pull-up/pull-down resistor, pad keeper, normal/ schmitt
• output and bi-directional with slew rate control
• silicon proven esd and latch-up structures
• fully contacted well ties
• analog power pads, crystal pads
• open architecture developers kit available

pll compilers

• programmable input, output frequencies and duty cycle
• input frequency range: 20 mhz - 200 mhz
• output frequency range: 50mhz -900mhz
• pll module entirely located in the i/o pad rings
• dedicated analog power supply pins
• build-in esd and latch-up protection structures

single port synchronons sram and two port register file compilers

• synchronous reads/writes
• static design with zero standby current
• byte write capability
• routable over the core with higher metal layer
• ability to compile to multiple aspect ratio
• ascan and bist support

faraday 0.18um gii library
standard cell

• 400 high performance standard cells
• 9-track cell architecture
• average cell density >120k gates/sq.mm
• optimized multiple drive strengths
• high porosity and routability
• scan version of every flip-flop available
• ultra low power cell available
• gated input for preventing leakage
• fully tool models support

inline and staggered i/o

• 1.8v, 3.3v i/o pads
• 1.8v/2.5vt, 3.3v/5vt i/o pads
• support over 500 io functions
• pad pitch: 65um (in-line), 40um (stagger)
• programmable current drives and slew rate control from 2ma to 16ma
• programmable pull-up/pull-down resistor, normal/ schmitt trigger
• provide 90 programming features in one i/o
• in-line to staggered i/o corner available

single port sram, dual port sram, one port register file, two port register file, and via2 rom compilers

• synchronous reads/writes
• static design with zero standby current
• byte write capability
• provides both high speed and low power srams
• ability to compile to multiple aspect ratio
• scan and bist support
• power port connections support
• zero hold time for inputs

faraday 0.18um ll library
standard cell

• 400 high performance standard cells
• 9-track cell architecture
• average cell density >120k gates/sq.mm
• optimized multiple drive strengths
• high porosity and routability
• scan version of every flip-flop available
• ultra low power cell available
• gated input for preventing leakage
• fully tool models support

inline and staggered i/o

• 1.8v, 3.3v i/o pads
• 1.8v/2.5vt, 3.3v/5vt i/o pads
• support over 500 io functions
• pad pitch: 65um (in-line), 40um (stagger)
• programmable current drives and slew rate control from 2ma to 16ma
• programmable pull-up/pull-down resistor, normal/ schmitt trigger
• provide 90 programming features in one i/o
• in-line to staggered i/o corner available

single port sram, dual port sram, two port register file and via1 rom compilers

• synchronous reads/writes
• static design with zero standby current
• byte write capability
• provides both high speed and low power srams
• ability to compile to multiple aspect ratio
• scan and bist support
• zero hold time for inputs

verisilicon 0.18um library (hjtc 0.18um logic 1p6m salicide 1.8v/3.3v process)
high-density standard cell

• wide variety of cell functions and drive strengths.
• process-specific optimization for high-density, high-speed, and low-power.
• engineered for synthesizability and routability.
• scan flip-flops for design for testability support.

i/o cell

• 3.3v i/o, 1.8v core, 5v tolerant.
• both inline and stagger compatible io pads.
• configurable input-output and skew rate control.
• robust esd (>2000v) and latch-up immunity (±200 ma). competitive pad pitch and height.

single-port / dual-port sram compilers

• ultra-high density, high-speed, and low-power.
• fully static operation and automatic power down.
• adaptive self-time delay for fast access time.
• full suite of design views and models.

diffusion rom compiler

• ultra-high density, high-speed, and low-power.
• fully static operation and automatic power down.
• automatic code implementation.
• high capacity configuration.
• full suite of design views and models.

two-port register file compiler

• ultra-high density, high-speed, and low-power.
• fully static operation and automatic power down.
• adaptive self-time delay for fast access time.
• full suite of design views and models.

supported design tools

virage logic 0.18um memory compiler

artisan 0.18um library
standard cell

• 1000 high performance standard cells
• 9-track cell architecture
• average cell density of 73k gates/sq.mm
• multiple drive strengths
• silicon proven
• scan version of every flip-flop available
• compatible with mixed signal environment
• accurate timing and power models

in-line and staggered i/o

• 3.3v/5vt
• pad pitch: 76.8um (in-line), 38.4um (staggered)
• multiple current drives up to 16ma
• pull ups, pull downs, switchable
• hysteresis
• built-in level shifting