0.25 micron libraries-英国威廉希尔公司

0.25 micron libraries

we have helped to revolutionize the foundry industry by offering comprehensive free-of-charge libraries from multiple vendors. in addition, hjtc also offers other libraries available on a fee basis.

virtual silicon 0.25um library
standard cell

• 500 high performance standard cells
• 11-track cell architecture, performance optimized for 150~400 mhz
• average cell density of 45k gates/sq.mm
• multiple drive strengths
• hand-crafted layout
• scan version of every flip-flop available
• fully contacted well ties
• accurate modeling and characterization for timing and power

two port register file

• synchronous reads/writes
• static design with zero standby current

inline i/o

• 70 3.3v i/o pads
• pad pitch: 60um
• multiple current drives up to 24ma
• input buffer types - pull-up/pull-down resistor, pad keeper, clock driver and normal/schmitt
• output and bi-directional buffer types with slew rate control
• silicon proven esd and latch-up structures
• automated eda views
• routable over the core with higher metal layer

verisilicon 0.25um library (hjtc 0.25um logic 1p5m salicide 2.5v/3.3v process)
high-density standard cell

• wide variety of cell functions and drive strengths.
• process-specific optimization for high-density, high-speed, and low-power.
• engineered for synthesizability and routability.
• scan flip-flops for design for testability support.

i/o cell

• 3.3v i/o, 2.5v core, 5v tolerant.
• both inline and stagger compatible io pads.
• configurable input-output and skew rate control.
• robust esd (>2000v) and latch-up immunity (±200 ma).
• competitive pad pitch and height.

single-port / dual-port sram compiler

• ultra-high density, high-speed, and low-power.
• input frequency range: 20 mhz - 200 mhz
• fully static operation and automatic power down.
• pll module entirely located in the i/o pad rings
• adaptive self-time delay for fast access time.
• full suite of design views and models.

diffusion rom compiler

• ultra-high density, high-speed, and low-power.
• fully static operation and automatic power down.
• automatic code implementation.
• high capacity configuration.
• full suite of design views and models.

two-port register file compiler

• ultra-high density, high-speed, and low-power.
• fully static operation and automatic power down.
• adaptive self-time delay for fast access time.
• full suite of design views and models.

supported design tools

faraday 0.25um library
standard cell

• 400 high performance standard cells
• 8-track cell architecture
• average cell density >60k gates/sq.mm
• optimized multiple drive strengths
• high porosity and routability
• scan version of every flip-flop available
• ultra low power cell available
• gated input for preventing leakage
• fully tool models support

inline and staggered i/o

• 2.5v, 3.3v i/o pads
• 2.5v/3.3vt, 3.3v/5vt i/o pads
• support over 500 io functions
• pad pitch: 65um (in-line), 40um (stagger)
• programmable current drives and slew rate control from 2ma to 16ma
• programmable pull-up/pull-down resistor, normal/ schmitt trigger
• provide 90 programming features in one i/o pad
• in-line to staggered i/o corner available

single port sram, two port sram, diffusion and via2 rom compilers

• synchronous reads/writes
• static design with zero standby current
• byte write capability
• provides both high speed and low power srams
• ability to compile to multiple aspect ratio
• scan and bist support
• power port connections support
• zero hold time for inputs