given the deep sub-micron design challenges that circuit designers are facing, hjtc reference design flows provide its customers with silicon-proven design methodologies that reduce time-to-volume by enabling manufacturability. the hjtc reference design flows incorporate 3rd-party eda vendor's baseline design flows to address issues such as timing closure, signal integrity, leakage power and design for manufacturability and adopts a hierarchical design approach built upon silicon validated process libraries. the hjtc reference design flows cover from schematic/rtl coding all the way to gds-ii generation and support cadence, mentor, springsoft and synopsys eda tools.
key benefits to customers
the hjtc reference design flows minimize or eliminate any library, technology, tool and flow issues prior to customers' using the libraries, pdk/foundry design kits (fdk) or tools in their design process and predict how their silicon really behaves. in brief, it significantly shortens:
time-to-tape-out
time-to-market
time-to-volume
supported technologies
the design flow will support hjtc l180 technologies using tools from eda partners including cadence, mentor, springsoft and synopsys and hjtc's design library, document, spice models and drc/lvs/extraction decks for digital designs.
technology/vender support for digital reference flow
| vender/technology | 180nm |
| hjtc-ees | datasheet * |
* myhjtc account is required.