drc questions
the purpose of drc (design rule check) sign-off is to verify customer's layout to meet hjtc's design rules. some customers adopt different libraries or embed customized blocks in their designs. in order to make sure the layout of a customer's design is acceptable by hjtc's layout rules, hjtc has come up with a drc sign-off flow. it was developed by cds/engineers, msd/ customer engineers and fab/pei engineers.
when a drc violation is found in the sign-off procedure, it will be either passed to the customer through his hjtc ce or reviewed by fab pei engineers. the drc sign-off is an important procedure for foundry service to improve production yield and avoid potential problems caused by possible layout rule violations.
design rule check sign-off flow
hjtc uses gds file name, date of file, top cell name and file size to identify the customer database and a file id is assigned to each database. so file size is a key item to check the correctness of the database in case of any data losses during file transferring.
yes, there is a metal coverage rule check that must be satisfied.
the requirement varies according to process. metal coverage check is included in hjtc drc command files. service of transparency checks of masks and dummy metal placement are provided by the hjtc mask tooling engineer (mte) and the mask house.
hjtc does not include the "antenna rule check" in the dracula command file because it cannot recognize the geometry of diodes connecting to the net of antenna concern . hjtc would like to prevent the customer from running into trouble due to dracula's limitations when building up the connection information. cadence has issued an internal pcr (no. 482163) to fix this problem. antenna check is not supported by diva because diva is a tool for cell-level/macro-level verification.
what happens if a customer needs the antenna rule check?
ans. hjtc antenna check is supported by calibre/mentor graphics, hercules/synopsys and has implemented into drc command files respectively. hjtc also provides trial-run service by calibre.
note: antenna rule check on calibre and hercules does not have this problem.
layer-marking is one of the approaches to execute the whole chip drc on an embedded memory cell in a design. it requires a very careful work on the boundary conditions for mask marking and is commonly used by vendors.
hjtc prefers using memory marker-layers where memory mark layers are well-defined in hjtc embedded memory database. in drc files, 2 sets of the rule checks are applied to logic portion and cell portion respectively and differentiated by the mark layers. with memory marker layers, the violations at memory area are eliminated so that the violations at other area can be reviewed completely.
it's not recommended due to boundary violations although their shapes are similar to memory marker layers'. some memory compilers that are out-of-date can't generate memory marker layers. for those memory cells without memory marker layers, it can reduce the violations and expedite the drc review by using opc layers as memory marker layers.
1. hjtc keeps the version of drc command files match the parent documents. the internal drc qa flow is shown at the next page.
2. drc qa patterns are updated right after the tlr is revised and applied to validating drc command files.
3. hjtc libraries and sram cells are also applied. drc qa patterns, hjtc libraries and sram cells are noted as qa database in the drc qa flow.
4. the programming engineers are asked to update drc command files once a bug is found in drc sign-off. the qa patterns are also updated for the new corner case.
1. hjtc supports assura for 0.35um and below technology.
2. vampire is not supported.
3. diva is not supported.
hjtc uses following interpretation for metal overlap via rule:
acceptant criterion of "metal enclosure (of via) in line-end direction by 0.1um"
is defined as -
1. metal overlap via by 0.1um in x-direction ( x and -x) or
2. metal overlap via by 0.1um in y-direction ( y and -y).
in other words, the direction where metal extends in both opposite sides of via is treated as the direction of the line.
marker layers are applied to the identification of fuse, pad, esd, dummy and slot. without marker layers, the specific drc rules such as fuse drc rule will not be applied to the target area and will check nothing. for the marker layer names and corresponding gds layer numbers, please refer to tlr, global rule and hjtc official layer mapping file.